1. Field of the Invention
The present invention relates in general to a burst page access unit for successively accessing a series of data in a semiconductor memory device, and more particularly to a burst page access unit which is capable of rapidly accessing a series of data in a semiconductor memory device to increase the operation speed and bandwidth of the semiconductor memory device.
2. Description of the Prior Art
Generally, semiconductor memory devices such as a dynamic random access memory (referred to hereinafter as DRAM) and a static random access memory (referred to hereinafter as SRAM) comprise a burst page access unit to enhance data read and write speeds. The burst page access unit is adapted to designate a memory cell array in response to an external row address signal and then to sequentially designate memory cells in the designated memory cell array in response to external successive column address signals.
However, whenever the burst page access unit is applied with an external column address strobe signal CAS, it receives the column address signal to designate the corresponding memory cell. For this reason, the burst page access unit has a very long access time because of the column address signal input period and the latent period required in designating the corresponding memory cell in response to the inputted column address signal
Recently, a synchronous DRAM has been developed to enhance the data access speed. The synchronous DRAM is adapted to write data in memory cells or to read data therefrom synchronously with an external clock signal. A conventional burst page access unit for the DRAM and SRAM may be used in the synchronous DRAM to access a series of data therein. However, the use of the conventional burst page access unit in the synchronous DRAM causes the data access time to become longer due to the synchronization with the clock signal.